1. Field
The current disclosure relates to method and apparatuses for packet processing, and more particularly, to methods and apparatuses for performing packet processing operations using distinct threads implemented in a single processing core to process different types of packets.
2. Background
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Packet processing operations can be divided into two different types. A first type includes operations performed by a control plane. These control plane operations include, for example, operations to control various aspects of the overall packet processing operation, including management of network devices, etc., as well as to generate rules used for packet processing. A second type includes operations performed by a data plane. These data plane operations relate to the processing of the data itself, for example, operations such as forwarding, modifying, and routing the data.
A conventional technique implements control plane operations and data plane operations using at least two separate central processing units (CPUs), with at least one of the CPUs being configured to perform control plane operations and the other at least one of the CPUs being configured to perform data plane operations.